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Going on with LPCXpresso

Created on 02-oct-2013 - Updated on 24-déc-2014 - 9550 views

LPC11xxLPCXpresso version 6

LPCXpresso version 6 is available. Installing it is as easy as installing version 5.

Slight modification of the default configuration, as I prefer using Chrome instead of Safari: in LPCXpresso / Preferences... / General / Web Browser, I add Chrome, with %URL% as parameter.

Another modification: I configure my own source file header comment, using LPCXpresso / Preferences... / C/C++ / Editor / Templates / comment (on OS X. I guess on Windows, it's Window / Preferences... / ...)

LPC111x characteristics

Having developed my first (small, simple) functional project, I need now to spend some time in looking at fundamental characteristics of the LPC1115 I use. Writing code for microcontrollers is far from being something new for me. But that's the first time I use an ARM-based microcontroller. Before going further with projects I have in mind, I want to thoroughly understand its distinctive features. Only then, I'll adapt my cooperating components design pattern, and go on with my projects.

LPC1115 is a Cortex-M0 based MCU. The Cortex-M0 core implements ARMv6 architecture. So, I'll use following documents as reference ones:

Memory access atomicity

ARMv6-M architecture reference manual states that following processor accesses are atomic:

  • byte transactions
  • halfword transactions to 16-bit aligned locations
  • word transactions to 32-bit aligned locations

Code sequence atomicity

Cortex-M0 generic user guide provides some information about how to ensure atomicity of a code sequence: disable the handling of exceptions by the processor. To do this, MRS and MSR instructions, or CPS instruction can be used to modify PRIMASK register. Only exceptions with configurable priority are disabled: Reset, NMI and HardFault can't be disabled.

Ordering of memory accesses

For this point, Application Note 312 seems to be the most valuable document. It provides following information:

  • section 3.5: This simple implementation results in a reduced need for barriers in a number of situations when code is only intended to ever run on the Cortex-M0. All use of DMB is redundant due to the inherent ordering of all loads and stores on the Cortex-M0.
  • section 4 provides case-by-case details. Among them:
    • There is no need to use a memory barrier instruction between each normal data access in memories.
    • There is no need to use a memory barrier instruction between each step during peripheral programming or peripheral access.
    • There is no need to insert memory barrier instructions between each SCS access, or between an SCS access and a Device memory access. (NVIC access is an SCS access)

To summarize: memory barrier instructions are supported on the Cortex-M0, in order to provide code compatibility for higher end processors. There is no need to use such instructions, as long as code is OK with following architecture characteristics:

  • all loads and stores always complete in program order
  • all Strongly-ordered load/stores are automatically synchronized to the instruction stream
  • interrupt evaluation is performed on every instruction
  • interrupt evaluation is performed between a CPSIE instruction and a following CPSID instruction
  • NVIC side-effects complete after less than two instructions following an NVIC load or store
  • the maximum prefetch size is two instructions, plus a fetch of two instructions in progress on the bus
  • Device and Normal load/stores may be pipelined
  • MSR side-effects are visible after one further instruction is executed.

In case of any doubt while writing some code, refer to section 4 of the Application Note.

Clock

According to LPC111x Data Sheet:

  • The Internal RC oscillator (IRC) may be used as the clock source for the WDT, and/or as the clock that drives the PLL and subsequently the CPU. The nominal IRC frequency is 12 MHz. The IRC is trimmed to 1 % accuracy over the entire voltage and temperature range.
    Upon power-up or any chip reset, the LPC1110/11/12/13/14/15 use the IRC as the clock source. Software may later switch to one of the other available clock sources.
  • maximum CPU frequency: 50 MHz.

system_LPC11xx.c defines SystemCoreClock as being 48000000. It uses the system PLL to boost the external crystal frequency (12 MHz) to 48 MHz. See this page for an explanation of how the PLL is configured, easier to understand than the one in the User Manual. LPC_SYSCON->SYSAHBCLKDIV is set to 1.

Importing my 5.2 project

I have now to go on working on the project I initiated with 5.2 version. Before importing it, I import the right CMSIS core library, from the archive file that can be found in the Examples folder: /Applications/lpcxpresso_6.0.2_151/lpcxpresso/Examples/NXP/LPC1000/LPC11xx/LPC11xx_LatestCMSIS_Libraries.zip (I use the LPC1115 - the path is for OS X installation).

This LPC11xx version is derived from ARM's CMSIS version 3.20. Provided files are summarized here.

Using File / New / LPCXpresso C Project, I create an LPC11xx C Project (Semihosted), using the project wizard. I choose to disable Code Read Protect. Once this empty project is created, I copy source files from my 5.2 project into this new project. That's it!

Flashing production release

After having spent some time testing and debugging my first application, I wanted to generate a production release, and to flash it. I found this way:

  • in Project / Build Configurations / Set Active, select Release
  • comment out any existing printf statement
  • in Quickstart Panel,  click on Build '<projectName>' [Release]
  • in the tool bar, click on the Program Flash icon pf, after having selected the axf file generated in the Release subdirectory. If you don't select it beforehand, no problem, you will be able to select it afterwards, from the Program Flash window.